This application is based upon and claims priority from prior French Patent Application No. 0001801, filed on Feb. 14, 2000, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The invention relates to the fabrication of integrated circuits and more particularly to the production of metal tracks using a process of the xe2x80x9cdamascenexe2x80x9d type, this being a name well known to those skilled in the art.
2. Description of the Prior Art
A damascene process may be carried out according to several methods of implementation. In the method of implementation called xe2x80x9csingle damascenexe2x80x9d, a track is produced by making a cavity in the intertrack dielectric lying at the metallization level in question and then, after having deposited a conducting barrier layer, for example made of tantalum nitride, on the bottom and on the sidewalls of the cavity, by filling the cavity with a filling metal.
The fabrication of the integrated circuit also includes the deposition of an encapsulation layer, typically made of silicon nitride, on the metallization level. This deposition is conventionally carried out at high temperature, typically at 400xc2x0 C. Moreover, apart from this heat treatment, the fabrication of an integrated circuit requires other heat treatments, for example after each oxide deposition. Now, during these heat treatments, and especially when depositing the silicon nitride at 400xc2x0 C., small quantities of silicon can diffuse into the copper tracks from the silicon nitride encapsulation layer. This then results in a significant increase in the resistivity of the metal tracks.
At the present time, this undesirable effect on the resistance of the tracks can be avoided by exposing the metallization level to an ammonia plasma before the silicon nitride encapsulation layer is deposited. This makes it possible to prevent a subsequent silicon diffusion. However, such a plasma-based treatment may damage the transistors of the integrated circuit.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above. The invention particularly aims to provide a solution to this problem discussed immediately above and proposes a radically different solution for avoiding the increase in the resistance of the metal tracks due to silicon diffusion into the copper.
A preferred embodiment of the present invention provides a process for fabricating an integrated circuit, comprising a step of producing, at a predetermined metallization level, at least one metal track within an intertrack dielectric material. This production step comprises the steps of etching the intertrack dielectric material so as to form a cavity at the position of the track, depositing a conducting barrier layer, for example made of tantalum nitride, in the cavity, filling the cavity with copper, and depositing a silicon nitride layer on the predetermined metallization level.
According to a general characteristic of the invention, the step of producing the metal track furthermore includes, between the barrier-layer deposition step and the copper-filling step, the deposition of titanium on at least part of the barrier layer.
Thus, when the silicon of the silicon nitride layer diffuses into the copper tracks, under high thermal budgets, for example greater than or equal to 400xc2x0 C., it forms a titanium silicide TiSi2 with titanium. The silicon which diffuses into the copper is thus trapped by the titanium, thereby allowing the low resistivity of the copper to be preserved.
In general, it is not necessary for the titanium layer to perfectly match the walls of the cavity nor for it to be perfectly continuous, since its sole purpose is to extract the silicon that has diffused into the copper therefrom (by transformation into titanium silicide). Thus, it is possible for this titanium deposition to be carried out by a simple sputtering operation, for example using an argon plasma which strikes a titanium target.
Moreover, the titanium sputtering deposition proves to be sufficient for depositing titanium particles on the upper part of the cavity, this having the advantage of being as close as possible to the silicon nitride layer.
According to one alternative preferred way of implementing the invention, prior to filling with copper, the titanium deposited in the cavity undergoes nonreactive ion etching with a plasma flux perpendicular to the bottom of the cavity. This allows the titanium in the bottom of the cavity to be removed and thus avoids the risk of increasing the resistance of the line (track). Furthermore, this non-reactive ion etching with a plasma flux perpendicular to the bottom of the cavity makes it possible to leave the plasma particles on the vertical sidewalls of the cavity, and in particular those close to the upper edge of the cavity.